Job Description
- Working experience in IP / SoC /Subsystem/verification
- Expertise to develop Soc/Top level verification environments using System Verilog and UVM
- Expertise to develop BFMs / Checkers / monitors / Scoreboards
- Must have developed block/system level verification plans and tests.
- Must have capability to debug test failures to find the root cause.
- Must have worked on code / functional coverage.
- Experience in constrained random testing is a plus.
- Domain skills : Any networking protocol/Ethernet/Pcie/CP
- Gate-level /SDFsimulations
- Knowledge of scripting languages like Perl, Tcl.
Contact Number: 99003 27273